1. Field of the Invention
This invention relates in general to a method for forming integrated circuit devices, and more specifically relates to a method for fabricating a transistor having a T-shape gate structure.
2. Description of the Related Art
Generally, a standard process for forming a transistor comprising forming a polysilicon gate, implanting ions to form source/drain regions and forming a gate silicide on the polysilicon gate. As the semiconductor technology trends to a higher integration, the device size significantly reduces. When the device size decreases the gate length thus reduces down below 0.2 .mu.m, and he resistance of the gate increases because the gate silicide has the same length as the underlying polysilicon gate. The increased resistance results in slowing down the speed and performance of the device due to RC delay.
Conventionally, one of the solutions to solve the increased resistance problem, such as disclosed by U.S. Pat. No. 6,096,590 issued to Chan et al., a metal gate longer than the polysilicon gate is formed over the polysilicon; namely a T-shape gate is formed to reduce the resistance of the gate. However, this procedure requires performing many steps of photolithography and highly alignment for forming the polysilicon gate first. Therefore, the process becomes complex and hard to control the produce yield rate, and furthermore manufacturing cost thus increases.